1. Field of the Invention
This invention relates to a cache memory device having two separate cache memories for data and instructions, and more particularly to a cache memory device for executing high-speed access while keeping consistency in self-correcting codes.
2. Description of the Related Art
It is desired that memory devices used in a computer be of fast and large capacity type. Since a fast memory device is generally expensive it is economically difficult to construct all the memory devices by means of fast-type memory devices only. Therefore, in general, a large capacity, inexpensive memory device and a small capacity, fast memory device are combined to equivalently realize a fast, large capacity memory. In this case, the small capacity, fast memory device is called "cache memory" (buffer storage).
The cache memory is disposed between a processor and a large-capacity main memory. The cache memory is adapted for temporarily storing data and/or instruction codes which are frequently transferred between the processor and the main memory. If data and/or instruction codes the processor is going to access are in the cache memory, then the processor accesses the cache memory in lieu of the main memory. This is called "cache hit". Namely, by storing data and/or instruction codes having high access frequency in the cache memory high-speed access can be achieved.
The structure of cache memory is divided into the following two types. The first type includes only one cache memory which buffers both data and instruction codes the processor handles. The second type includes two separate cache memories, one for storing data and the other for storing instruction codes. Having limited capacity, the cache memory is updated as needed so that data and/or instruction codes having higher access frequency are always stored therein.
As in the case of the second type, when the cache memory is divided into a data cache memory and an instruction cache memory mutual interference can be avoided which might occur between data and program in the algorithm for refreshing the contents of the cache memory. In other words, the contents of each of the data cache memory and the program cache memory (which is also referred to as "instruction cache") can be optimized. Further, where the processor has separate data-access and instruction-fetch ports, they can be used simultaneously and in parallel with each other.
However, disadvantages will also arise from the division of the cache memory into the data cache and the instruction cache. That is, in the case of operation in which the program changes itself while running, or in the case of so-called self-changing code, the consistency in data, or instruction codes, or processing will be lost between both the cache memories, and between each cache memory and the main memory. In other words, the operation for the program to rewrite itself is an operation intended for the data cache memory in which the program is handled as if it is data. On the other hand, the operation for the processor to execute the rewriting of program is an operation applied to the instruction cache memory in which instructions are fetched from the instruction cache memory. Namely, until an instruction written into the data cache memory is returned (write back) to the main memory, a content fetched from the main memory when the instruction is executed is not subjected to any change. It is also true of the case where the instruction has been entered into the cache memory before the content is changed. Conventionally, to avoid such a problem, a program to be subjected to the self-change is not entered into the cache memory but entered into the main memory. Naturally, in this case, the advantage of the cache-memory's capability of high-speed processing cannot be expected so that the execution of program is lowered in speed. However, the self-changing program is often used primarily for making the operation of the program itself fast. Thus, the fact that a cache memory cannot be used for storing the self-changing program results in a great disadvantage. To obviate this, large hardware generally called a bus watch is required to always monitor the access conditions.
Typical artificial intelligence languages such as Prolog and Lisp operate in their execution processes as if they executed programs while producing them. Thus, the technique of the self-changing program is essential to these languages.
For this reason, a cache memory device is desired which has a data cache memory and an instruction cache memory independently, and can keep consistency between the cache memories and between each cache memory and main memory with respect to a self-changing program as well.
As described above, with the conventional cache memory device of data cache and instruction cache separation type, problems arise in which the consistency in the execution of the self-changing code cannot be held, the self-changing code cannot cached, or large hardware is required to monitor the caches.